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模拟芯片验证工程师 / Mixed Signal DV Engineer 德州仪器半导体技术(上海)有限公司 上海-浦东新区 10-23

学历要求:本科|工作经验:2年|公司性质:外资(欧美)|公司规模:150-500人

Responsibilities:Mixed Signal Design Verification Engineer capable of the following responsibilities:Execute the pre-silicon verification of mixed-signal products? Create verification plans using datasheets, inputs from engineers/customers, and working closely with systems engineers. ? Implement mixed-signal test-benches in Cadence Virtuoso and/or Verilog-AMS to apply stimulus and checks. ? Implement automatic checks and measurements to verify DUT behavior and populate a Spec Compliance Matrix (SCM). ? Provide periodic updates on DV status to project participants, management, and customers.? Work with design and systems teams to close bugs as they arise.? Drive new and improved methodologies where needed, work with the EDA team to upgrade tools and flows.? Review the digital and analog design to provide guidance on Design for Verification architecture and features.Requirements:- One of Verilog-A or Verilog-AMS or SystemVerilog or Specman or Verilog- Analog transistor-level design or simulation experience-Mixed-signal AMS experience using the Cadence-based solution (irun+spectre or irun+ultrasim, etc.)in addition to :? Creating behavioral models of analog circuits? Understanding of Constrained-random stimulus and auto-checking verification environments? Familiar with Bug tracking, functional coverage? Cadence Virtuoso schematic editor and ICFB tool environment? Project management, time management, multi-tasking, problem solving and communication (written and oral)

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IC应用工程师(开关电源类) 辰芯半导体(深圳)有限公司 深圳-宝安区 1-2.5万/月 10-23

学历要求:本科|工作经验:3-4年|公司性质:民营公司|公司规模:少于50人

岗位和职责:1. 产品验证:负责相关IC的系统功能验证、应用故障排查分析, 协助并参与撰写和检查相关IC的应用参考等技术文档;2. 产品培训:协助准备产品推广所需材料, 对市场销售人员和分销商现场应用工程师进行培训;3. 方案提供:根据客户的要求,与设计部门沟通并提供合理方案;4. 技术支持:负责产品应用问题的技术支持及客诉处理;5. 客户维护:与代理商及客户保持及时沟通,挖掘产品需求并将新的产品信息反馈给设计部门;6. 行业报告:收集、掌握主流竟争对手产品相关性能、优劣势等,并形成分析报告。任职要求:1.电子类相关专业,本科及以上学历;2. 熟悉模拟、数字电路理论基础;3.熟悉开关电源拓扑结构,设计测试等环节,5年以上相关工作经验;4. 会使用电路设计相关软件如OrCAD, Pads PCB, Pads logic, AD, Protel等;5. 熟练使用万用表,示波器等常用电子测量设备;6. 了解单片机工作原理和软件架构;7. 责任心强,能承受一定的工作压力,严谨细致,积极主动,具有团队合作精神;8. 具有良好的沟通表达及分析解决问题的能力;9. 具有良好的文档编写及英语读写能力。一但录用,我们会为您提供:1、完善的假期组合上班时间5天7.5小时工作制(上午09:00-12:00 下午13:30-18:00)2、福利、丰富多彩的员工生活社保、公积金、法定节假日、不定期公司会组织员工参加户外活动、旅游、过节礼品/礼金、生日会、唱K、下午茶、聚餐等。工作地点:深圳市宝安区新安街道创业路东联大厦B506(地铁五号线洪浪北B出口50米)联系人:朱小姐 ,联系方式: 18086036231.

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NVE Product Verification Engineer 美光半导体技术(上海)有限公司 上海 10-23

学历要求:|工作经验:|公司性质:外资(欧美)|公司规模:500-1000人

Job DescriptionAs a Non-Volatile Engineering (NVE) Product Verification Engineer at Micron Technology, Inc., you will be responsible for product qualification executions and customer issue analysis, including test programs development, failure analysis, data analysis of eMMC/MCP memory devices. You will create and maintain product documentation, ensure necessary resources, analyze product data and respond to product line and customer issues. You will work closely with Quality Assurance, Development, Applications Engineering and HVM PE to ensure product reliability and provide customer support. You will also be asked to gain new product knowledge, as well as develop and mentor talent. Responsibilities and TasksManage New Product qualification Execution-facilitate and manage qualification execution-develop qualification test program/sequence based on specifications and application usage model-Perform Electrical Failure Analysis (EFA) and drive root cause and corrective action with other internal engineering groups-Analyze results to identify marginalities-Report data in a clear format including concise comments about findings-Perform risk assessment at all decision points within qualification cycle-Collaborate to develop the DFMEA (Design Failure Mode Effect Analysis), DFT (Design For Testability), DFM (Design For Manufacturability) Develop and execute TFW for production, FA and NAND verification-Develop clean code targeting embedded NAND and integrate with firmware developed by other team members-Create unit tests and integrate with automation frameworks-Aid in creation of test plans and assist in test activities related to characterization-Developing application level firmware and hardware libraries on a Cortex-M based processor using C and C++ Ensure readiness of Failure Analysis Support for Managed NAND products-Maintain knowledge of product functionality-Identify suitable testing equipment-Develop software and hardware tools-Build collaborative relationships with Design Team (ex. silicon, controller, firmware) Support Investigations of Customer Issues-Comprehend the issue (examples: failure mode, usage conditions)-Replicate the issue on testing equipment-Identify root cause-Work with Quality Assurance Teams on customer returns to establish root cause and corrective actionSupport Design-in Activity for External Stakeholders -Support marketing application engineering with failure analysis-Collaborate with the marketing application engineering team to manage application notes, risk assessment, and “errata” versus datasheet-Define solutions with Development team-Support to solve issues during proliferation design-in and customer mass productionProvide Technical Training and Expertise-Provide On-the-Job Training (OJT) for new Engineers-Instruct on data presentation and techniques-Assist with data interpretation-Attend technical seminarsRequirements:RCG of Electrical engineering or Microelectronics background with BS or MS degree at Electronics or semiconductor fieldExperienced on programming language of C/C++, familiar with script language like perl, pythonGood at analytic and problem solving skillsGood ability to work in a team environment and communicate effectively with team membersFluent in English writing and oral communicationWe recruit, hire, train, promote, discipline and provide other conditions of employment without regard to a person's race, color, religion, sex, age, national origin, disability, sexual orientation, gender identity and expression, pregnancy, veteran’s status, or other classifications protected under law. This includes providing reasonable accommodation for team members' disabilities or religious beliefs and practices.Each manager, supervisor and team member is responsible for carrying out this policy. The EEO Administrator in Human Resources is responsible for administration of this policy. The administrator will monitor compliance and is available to answer any questions on EEO matters.To request assistance with the application process, please contact Micron’s Human Resources Department at 1-800-336-8918 (or 208-368-4748).职位要求:详见职位描述

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射频测试工程师 深圳骏通微集成电路设计有限公司 深圳 6-8千/月 10-23

学历要求:本科|工作经验:|公司性质:民营公司|公司规模:少于50人

岗位职责负责有关射频产品的测试工作。认真谨慎地制定测试方案,从测试到最终测试报告的完成。为射频产品的应用提供解决的办法。通过提供技术支持,寻求***的问题解决方式以满足客户需求。能力要求本科学历,电磁场与微波、电子工程或通信工程等相关专业;具备射频电路与系统相关知识;熟悉频谱仪、网络分析仪、信号发生器等常用射频测试仪器;能根据测试要求制定测试计划,完成测试工作;熟练使用PCB板设计工具,如Protel,PowerPCB等;做事细心,有耐心,沟通能力强,有团队合作精神和协调能力。

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集成电路设计/验证工程师 国微集团(深圳)有限公司 深圳 1-1.5万/月 10-23

学历要求:本科|工作经验:无工作|公司性质:外资(欧美)|公司规模:150-500人

岗位要求:1、微电子、集成电路及电子工程相关专业,本科或硕士; 2、熟悉数字电路设计,熟练掌握Verilog; 3、有实习项目、科研项目经历者优先; 4、英语六级; 5、有良好的文档编写能力。岗位职责:1、芯片数字模块的设计,RTL编码实现和模块级验证; 2、详细设计和用户手册等文档的编写和维护。

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FPGA逻辑工程师 四川赛狄信息技术股份公司 成都-高新区 1.5-2万/月 10-23

学历要求:|工作经验:|公司性质:民营公司|公司规模:150-500人

工作职责1、根据部门的相关制度及流程,确认产品的大逻辑需求;2、负责逻辑(FPGA)设计;3、负责大逻辑测试及产品联试工作;4、负责技术支持工作;5、上级交办的其他工作。任职资格1、电子工程、通信工程、自动化等相关专业,本科或以上学历,能够熟练阅读和理解英文资料;2、具有DDR2、DDR3、RapidIO、PCIE等高速接口调试经验优先;3、有FPGA设计经验; 熟练掌握Verilog/VHDL语言,具有较为复杂的逻辑设计经验,优良的RTL代码风格;4、熟悉XILINX或ALTERA FPGA内部结构,熟悉相关开发工具(ISE,Quartus II, synplify,ModelSim等)和流程;5、具有一定的系统验证和调试经验,能够根据设计目标确定仿真验证和调试测试点;6、对数据采集、信号处理和数学建模有良好的理论知识和应用经验优先,如AD/DA、DUC/DDC、CFR等等;7、有军工行业从业背景者优先;8、具有良好的学习意识、团队意识、沟通能力、敬业精神。

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数字电路设计工程师 普冉半导体(上海)有限公司 上海-浦东新区 1-2万/月 10-23

学历要求:本科|工作经验:|公司性质:民营公司|公司规模:50-150人

岗位描述1.负责数字电路模块SPEC的理解及分解2.采用Verilog/System Verilog进行数字电路RTL代码编写3.负责模块级电路的仿真验证Plan的制定及模块级电路的仿真验证4.模块级综合及时序分析。"岗位要求1.了解Makefile和Perl或Photon2.熟悉Verilog/Systemverilog语言3.了解PrimeTime/DesignCompiler/Ncverilog等工具3.了解UVM验证平台4.了解Matlab或C、C++5.具有结构性思维6.微电子、计算机、通信专业本科及以上"Job Description1.Digital Module spec scripts2.RTL coding by verilog/system-verilog3.Module simulation plan and testbench setup, simulation and debug4.Ciruit compiler by DC and timing analysis by PrimeTime"Job Requirements1.Basic knowledge of Makefile and Perl2.Basic knowledge of System-Verilog and UVM3.Basic knowledge of EDA tools such as: Design Compiler/PrimeTime/Ncverilog 4.Basic knowledge of Matlab or C or C++5.Sense of Logic Architecture6.BS or Above Majored in EE or Computer or Communication"

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数字IC设计工程师 启攀微电子(上海)有限公司 上海-闵行区 15-25万/年 10-23

学历要求:本科|工作经验:2年|公司性质:外资(欧美)|公司规模:50-150人

职位描述:负责模块级体系结构设计, 描述设计文档, 数字电路的设计, 仿真, 验证以及综合工作 .职位要求:电子工程、通信、微电子等相关专业本科或本科以上学历;本科或硕士一年以上设计经验;熟悉IC设计流程, 包括电路设计,验证, 综合, DFT, STA, 形式验证等;优先考虑具有芯片开发经验者;良好的英文读,写能力;良好的团队合作性,责任心以及沟通能力.

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设计数字验证工程师DV 牡丹忆芯科技有限公司 贵阳 1-2万/月 10-23

学历要求:硕士|工作经验:5-7年|公司性质:民营公司|公司规模:50-150人

1. 负责制定高覆盖率的芯片/模块验证计划; 2. 用System Verilog以及UVM验证方法学进行模块以及全芯片的功能验证; 3. 利用仿真,FPGA和Emulator进行性能分析和验证; 4. 执行带时序的后仿真工作; 5. 为芯片测试工程师提供测试机测试向量; 6. 在SOC芯片中利用固件代码(C语言)进行芯片测试; 7. 帮助FPGA工程师搭建并调试芯片/模块的FPGA验证环境 。 任职要求 1. 电子工程专业或计算机专业本科或以上学历,3年以上IC设计/验证经验; 2. 熟悉IC设计流程; 3. 熟练掌握Cadence,Synopsys,Mentor逻辑仿真工具; 4. 熟练掌握Verilog和System Verilog; 5. 对覆盖率模型,带约束的随机向量生成等验证方法学有很好的理解(UVM,VMM,OVM); 6. 有较好的基于SOC的C编程基础; 7. 最好熟悉PCIe,NVMe、DDR和Flash相关技术。

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图形芯片验证资深工程师 成都海光集成电路设计有限公司 上海-浦东新区 4-4万/月 10-23

学历要求:|工作经验:|公司性质:民营公司|公司规模:150-500人

图形芯片验证资深工程师 岗位职责: – 根据设计规格,提取功能点和测试点,设计和编写测试用例,完成验证计划编写 – 理解芯片和模块功能,开发直接和随机测试激励,开发各种monitor和checker ,BFM以及assertion – 调试各种testench 和testcase 失败案例,与设计工程师一起修复并验证bug – 执行验证计划,进行回归测试,确保代码覆盖率和功能覆盖率达到tape out 要求 – 维护并改善testbench和验证流程,评估或采用最新工具和方法 – 协助软、硬件设计人员开展软、硬件相关调试工作 任职要求: – 电子工程、微电子或相关专业,本科或硕士9年以上相关工作经验 – 熟练掌握Verilog, SV, C/C++, SystemC等语言 – 熟悉testbench结构和验证方法学,比如UVM,OVM或VMM – 熟悉ASIC验证流程和常用EDA 仿真、调试工具 – 较强的script 能力,比如Perl, Python, Ruby,Unix Shell,或相关语言 – 参与过大规模并行运算验证,大型Server 级芯片验证,多核 CPU,GPU 或 AI芯片验证经验者优先 – 熟悉performance verification, power verification 优先 – 较强的解决问题能力,良好的沟通能力和团队协作能力 – 良好的英文文档阅读与撰写能力 Graphic Chip Design Verification Senior Engineer Responsibility: Write or update design spec according to architecture changes. – Understand chip level and block level function, create testplan, improve testbench and methodology – According to chip/block function, create direct and random test cases with C/C++/SV, as well as various monitors and checkers, and assertions – Debug various testbench and testcase failures, find out root cause dependently, support designer to fix and verify bugs. – Execute testplan, run regression, achieve code coverage and function coverage goal before tape out – Maintain and improve testbench and verification flows with better efficiency, evaluate and adopt latest verification tool or flow. – Take part in all phases of chip development, support hardware and software engineer to debug hardware or software issues Requirement: – BS or Master with at least 9 years of ASIC design. – Proficient in Verilog, SV, C/C++, SystemC etc – Familiar with testbench structure and methodology, like UVM, OVM, or VMM. – Familiar with popular EDA simulation & debug tools – Good experience in scripting languages like Perl, Python, Ruby, Unix shell or similar languages. – Experience on large scale of parallel computing, big server, multi-core CPU, GPU or AI chip is big plus – Experience of performance verification, power verification is big plus – Strong problem solving, communication skills and good team work spirit – Good English skill of document reading and writing 

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